1. Field of the Invention
The present invention relates to a high-speed synchronous multiplexing apparatus, and particularly to an SDH (synchronous digital hierarchy) apparatus having a high-speed device and a low-speed device, and further, to one that employs electrical signals to interface the high- and low-speed devices with each other.
The apparatus according to the present invention is able to apply the North American Standard SONET (Synchronous Opticall Network), wherein a STM (Synchronous Transport Module) signal is changed to a STS (Synchronous Transport Signal) signal, and a VC (VIrtual Container) signal is changed to a VT (Virtual Tributary) signal.
The SDH apparatus synchronously transmits frames of information, using optical signals, at a high speed. The SDH apparatus is required to reduce the scale thereof to minimize the cost and improve the performance thereof. To achieve this, an SDH apparatus that employs electrical signals to interface internal devices with each other is needed.
2. Description of the Related Art
FIG. 1 shows an SDH apparatus according to a prior art. The apparatus has a low-speed device 200 and a high-speed device 201 and uses optical signals to interface the devices 200 and 201 with each other.
The interfacing optical signals are optical STM-0 (Synchronous Transport Module level One, which corresponds to a STS-1 in the North American Standard) signals of 51.48 Mb/s as specified in the SDH standards. The "STM" is an abbreviation of "synchronous transport module."
FIGS. 2A and 2B show examples of the low- and high-speed devices 200 and 201 of the prior art of FIG. 1.
In the low-speed device 200, an optical-to-electrical converter converts a low-speed optical input signal into an electrical signal. An STM terminator terminates the electrical signal and separates an STM frame from the electrical signal. A pointer processor sets a pointer to indicate the position of data in the signal. A clock switch switches a clock signal attached to the input signal to an internal clock signal. A frame aligner aligns the STM frame. A pointer inserter inserts a pointer into the STM frame. An STM multiplexer prepares an electrical STM signal. An electrical-to-optical converter converts the electrical STM signal into an optical STM signal, which is transferred to the high-speed device 201. An optical signal from the high-speed device 201 to the low-speed device 200 is processed in the opposite way, to provide a low-speed optical signal.
In the high-speed device 201, an optical-to-electrical converter converts the optical STM signal from the low-speed device 200 into an electrical STM signal. An STM terminator terminates the electrical STM signal and separates an STM frame from the same. A pointer processor sets a pointer to indicate the position of data in the STM frame. A clock switch switches a clock signal attached to the input signal to an internal clock signal. A frame converter converts the STM frame into an internal frame. A high-speed multiplexer multiplexes such frames into an electrical STM signal. An electrical-to-optical converter converts the electrical STM signal into an optical STM signal, which is transmitted to another station. When the high-speed device 201 receives an optical STM signal from another station, an optical-to-electrical converter converts the optical signal into an electrical signal, and a high-speed demultiplexer demultiplexes the electrical signal into STM frames. Thereafter, the above-mentioned processes are carried out in the opposite way, and an optical signal is transferred to the low-speed device 200.
In this way, each of the low- and high-speed devices 200 and 201 of the prior art receives an STM signal, terminates the same, reassembles an STM signal, and transfers it to the opposite device. An interface in each device is, for example, VC32. After terminating an STM signal, the device processes a pointer to adjust the phase of the signal. The device detects a frame according to a frame pattern in the received STM signal. Each frame from the high-speed demultiplexer in the high-speed device 201 must be converted into an internal frame, which must be aligned, a pointer must be set in the frame, an STM frame must be reassembled accordingly, the STM frame must be converted into an optical STM signal, and then, the optical STM signal must be transferred to the low-speed device 200.
FIG. 3 shows switching a clock signal to another between the low-speed device 200 and the high-speed device 201 of the prior art.
The low-speed device 200 multiplexes a frame of data into an electrical signal based on an internal clock signal, converts the electrical signal into an optical signal, and transfers the optical signal to the high-speed device 201. The high-speed device 201 converts the optical signal into an electrical signal and extracts a transmission clock signal therefrom. Based on the transmission clock signal, the high-speed device 201 synchronizes a frame contained in the electrical signal, switches the transmission clock signal to the internal clock signal, and transfers the frame to another part of the high-speed device 201.
On the other hand, the high-speed device 201 multiplexes a frame of data into an electrical signal based on the internal clock signal, converts the electrical signal into an optical signal, and transfers the optical signal to the low-speed device 200. The low-speed device 200 converts the optical signal into an electrical signal, extracts a transmission clock signal therefrom, synchronizes a frame contained in the electrical signal based on the transmission clock signal, switches the transmission clock signal to the internal clock signal, and transfers the frame to another part of the low-speed device 200.
In this way, the reception interface of the prior art employs a clock signal extracted from an optical signal.
FIG. 4 shows alarm collecting and prioritizing processes of the prior art.
An alarm collector 210 collects alarms from packages in the SDH apparatus. A prioritizing unit 211 prioritizes the alarms. An alarm converter 212 converts the alarms into alarm outputs. An alarm interface 213 provides an external alarm collecting unit with an alarm signal accordingly.
The prior art carries out these alarm processes between the alarm collector 210 and the alarm interface 213 almost entirely by the use of software.
FIG. 5 shows a technique of supplying power according to the prior art.
A device unit 220 is provided with power units 221 and 222, which are separated from packages to which the units 221 and 222 supply power. Namely, the power units 221 and 222 are independent of the packages and are collectively installed in the device unit 220.
As explained above, the SDH apparatus of the prior art employs an optical interface between the low- and high-speed devices 200 and 201. Accordingly, each of the devices 200 and 201 must have the optical-to-electrical and electrical-to-optical conversion functions, STM termination function, and frame conversion function. These functions increase the scale of each device. The problems of the prior art employing the optical interface will be explained in more detail.
STM-0 signals are transmitted between the low- and high-speed devices 200 and 201 at a rate of 51.84 Mb/s. When processing the signals in series, each device may have a shortage of timing margin. The devices, therefore, must use ECL circuits, which increase power consumption and need a large space.
Using the optical interface between the devices 200 and 201 necessitates the functions of converting optical signals into electrical signals and STM frames into internal frames. These functions are realized with circuits that need a large space. The prior art uses for various processes the frame period of an upward input signal that travels in the direction from the low-speed device 200 to the high-speed device 201, and therefore, the high-speed multiplexer of the high-speed device 201 must absorb frame phases. Accordingly, the high-speed multiplexer must have large capacity and size.
The prior art terminates an external frame and converts the frame into an internal frame. Accordingly, the prior art must have large frame converters. The prior art synchronizes an STM-0 frame by scrambling and descrambling. This needs large circuits. The prior art must have the frame conversion function, frame aligning function, and STM multiplexing function in each of the low- and high-speed devices 200 and 201, thereby increasing the scale of the SDH apparatus. Since the interface between the low- and high-speed devices 200 and 201 is asynchronous as shown in FIG. 3, stuffing and clock switching functions are needed which increase the circuit scale.
To set apparatus parameters, the SDH apparatus of the prior art must have a controller. This also increases the scale of the SDH apparatus in terms of software and hardware. If the low- and high-speed devices 200 and 201 are disconnected from each other, the circuit involving them is unused. Alarms in the unused circuit hinder the detection of a fault during maintenance. However, these alarms must not simply be masked, because if an erroneous disconnection occurs and if a circuit switching alarm to cope with the disconnection is masked, the disconnected circuit will be left as it is without switching to another.
The prior art employs software to process alarms and cope with faults, as shown in FIG. 4. The high-speed device 201 handles many circuits and are, therefore, unable to satisfy required performance or specified processing time if the alarm process is entirely carried out by software. On the other hand, there are many decoded alarms, which are usually not transmitted by hardware, e.g., signal lines. If alarms are prioritized only by hardware decoding, an enormous number of changes will be involved whenever a change or an error occurs in the priority of alarms.
An alarm frequently causes chain alarms during maintenance. When prioritizing these alarms along a time axis, the prior art sometimes provides a useless priority result or an intricate priority process that needs an accumulation of alarms for a given period, depending on the order and timing of collecting alarms from packages.
The prior art collectively installs power sources in a given package in the SDH apparatus, as shown in FIG. 5. This hinders a hierarchical arrangement of packages that are designated for specific functions in the SDH apparatus.
The prior art also has a problem in connection with an electrical interface between packages. When a sender package transfers a signal to a receiver package that is made of a CMOS circuit, a source voltage transitionally increases when the receiver package is inserted or extracted. This results in increasing an input voltage above a voltage allowed for a reception buffer, to cause a latch-up phenomenon to break the buffer. When the prior art employs a high-speed clock signal of 25 MHz, wiring capacitance causes a bad influence. Namely, the pulse width of a frame pulse signal widens to cover two pulses of the clock signal.